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1 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 3v rs-232 serial transceiver with logic selector and15kv esd protection the sp3203e provides a rs-232 transceiver solution for portable and hand-held applica- tions such as palmtops, pda's and cell phones. the sp3203e uses an internal high- efficiency, charge-pump that requires only 0.1 f capacitors during 3.3v operation. this charge pump and sipex's driver architecture allow the sp3203e to deliver compliant rs-232 performance from a single power supply ranging from +3.0v to +5.5v. the sp3203e is a 3-driver/2-receiver device, with a unique v l pin to program the ttl input and output logic levels to allow interoperation in mixed-logic voltage systems such as pda's and cell phones. receiver outputs will not exceed v l for v oh and transmitter input logic levels are scaled by the magnitude of the v l input. 3 driver/ 2 receiver architecture logic selector function (v l ) sets ttl input/output levels for mixed logic systems meets true eia/tia-232-f standards from a +3.0v to +5.5v power supply i nteroperable with eia/tia-232 and adheres to eia/tia-562 down to a +2.7v power source minimum 250kbps data rate under load regulated charge pump yields stable rs-232 outputs regardless of v cc variations enhanced esd specifications: +15kv human body model + 15kv iec1000-4-2 air discharge + 8kv iec1000-4-2 contact discharge description applications palmtops cell phone data cables pda's sp3203e ? now available in lead free packaging t 1 in 1 2 3 4 17 18 19 20 5 6 7 16 15 14 shutdown v+ c1+ gnd v cc 8 9 10 11 12 13 t 3 in r 2 out t 2 in r 1 out v l sp3203e c 1 - c 2 + c 2 - v- t 1 out t 2 out t 3 out r 1 in r 2 in features
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 2 note 1: v + and v - can have maximum magnitudes of 7v, but their absolute difference cannot exceed 13v. absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. v cc ..................................................................-0.3v to +6.0v v + (note 1)..................................................-0.3v to +7.0v v - (note 1)...................................................+0.3v to -7.0v v + + | v - | (note 1).........................................................+13v i cc (dc v cc or current)........................................... +100ma input voltages txin, shutdown = gnd..........................-0.3v to +6.0v rxin............................................................................... +25v (v cc = v l = +3v to +5.5v, c1-c4 = 0.1 f, tested at +3.3v +10%, c1 = 0.047 f, c2-c4 = 0.33 f, tested at +5.0v +10%, t a = t min to t max , unless otherwise noted. typical values are at v cc = v l +3.3v, t a = +25 c.) electrical characteristics output voltages txout............................................................. + 13.2v rxout..............................................-0.3v to (v l + 0.3v) short-circuit duration txout................................................................continuous storage temperature...............................-65 c to +150 c power dissipation per packages 20-pin tssop (derate 7.0mw/ c above+70 c)............................560mw r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s c i t s i r e t c a r a h c c d v ( c c t , v 5 + r o v 3 . 3 + = a 5 2 + = o ) c t n e r r u c y l p p u s3 . 01a mv = n w o d t u h s c c d a o l o n , t n e r r u c y l p p u s n w o d t u h s10 1 a d n g = n w o d t u h s s t u p n i c i g o l w o l d l o h s e r h t c i g o l t u p n i 8 . 0 vn w o d t u h s , n i x t v l v 0 . 5 r o v 3 . 3 = 6 . 0v l v 5 . 2 = h g i h d l o h s e r h t c i g o l t u p n i 4 . 2 vn w o d t u h s , n i x t v l v 0 . 5 = 0 . 2v l v 3 . 3 = 4 . 1v l v 5 . 2 = 9 . 0v l v 8 . 1 = s i s r e t s y h t u p n i r e t t i m s n a r t5 . 0v t n e r r u c e g a k a e l t u p n i1 0 . 0 1 a n w o d t u h s , n i x t s t u p t u o r e v i e c e r s t n e r r u c e g a k a e l t u p t u o5 0 . 0 0 1 a d e l b a s i d s r e v i e c e r , t u o x r w o l e g a t l o v t u p t u o4 . 0vi t u o a m 6 . 1 = h g i h e g a t l o v t u p t u o v l - 6 . 0 v l - 1 . 0 vi t u o a m 1 - =
3 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation electrical characteristics (v cc = v l = +3v to +5.5v, c1-c4 = 0.1 f, tested at +3.3v +10%, c1 = 0.047 f, c2-c4 = 0.33 f, tested at +5.0v +10%, t a = t min to t max , unless otherwise noted. typical values are at v cc = v l +3.3v, t a = +25 c.) r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c s t u p n i r e v i e c e r e g n a r e g a t l o v t u p n i5 2 -5 2 +v w o l d l o h s e r h t t u p n i 8 . 05 . 1 vt a 5 2 + = o c v l v 0 . 5 = 6 . 02 . 1v l v 3 . 3 r o v 5 . 2 = h g i h d l o h s e r h t t u p n i 8 . 14 . 2 vt a 5 2 + = o c v l v 0 . 5 = 5 . 14 . 2v l v 3 . 3 r o v 5 . 2 = s i s e r e t s y h t u p n i5 . 0v e c n a t s i s e r t u p n i357k ? t a 5 2 + = o c s t u p t u o r e t t i m s n a r t g n i w s e g a t l o v t u p t u o5 4 . 5 v k 3 h t i w d e d a o l s t u p t u o r e t t i m s n a r t l l a ? . d n g o t t a 5 2 = o c e c n a t s i s e r t u p t u o0 0 3m 0 1 ? v c c v 2 = t u p t u o r e t t i m s n a r t , 0 = - v = + v = t n e r r u c t i u c r i c - t r o h s t u p t u o0 6 a mv t u o x t 0 = t n e r r u c e g a k a e l t u p t u o5 2 a v t u o x t ; d e l b a s i d r e t t i m s n a r t , 2 1 = v c c v 5 . 5 o t v 0 . 3 r o 0 = n o i t c e t o r p d s e r x t , n i x t u o n o i t c e t o r p d s e 5 1 v k l e d o m y d o b n a m u h 5 1 e g r a h c s i d p a g r i a 2 - 4 - 0 0 0 1 c e i 8 e g r a h c s i d t c a t n o c 2 - 4 - 0 0 0 1 c e i
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 4 electrical characteristics (v cc = v l = +3v to +5.5v, c1-c4 = 0.1 f, tested at +3.3v +10%, c1 = 0.047 f, c2-c4 = 0.33 f, tested at +5.0v +10%, t a = t min to t max , unless otherwise noted. typical values are at v cc = v l +3.3v, t a = +25 c.) note 2. transmitter skew is measured at the transmitter zero crosspoint. r e t e m a r a p. n i m. p y t. x a ms t i n us n o i t i d n o c e t a r a t a d m u m i x a m0 5 2s p b kr l k 3 = , ? c l , f p 0 0 0 1 = g n i h c t i w s r e t t i m s n a r t e n o y a l e d n o i t a g a p o r p r e v i e c e r t l h p 5 1 . 0 s t u p t u o r e v i e c e r o t t u p n i r e v i e c e r c l f p 0 5 1 = t h l p 5 1 . 0 e m i t e l b a n e t u p t u o r e v i e c e r0 0 2s nn o i t a r e p o l a m r o n e m i t e l b a s i d t u p t u o r e v i e c e r0 0 2s nn o i t a r e p o l a m r o n n w o d t u h s t i x e o t e m i t0 0 1 s v i t u o x t v 7 . 3 > i w e k s r e t t i m s n a r t i t l h p t - h l p i 0 0 1s n) 2 e t o n ( w e k s r e v i e c e r i t l h p t - h l p i 0 5s n e t a r w e l s n o i g e r - n o i t i s n a r t 60 3 / v s c l f p 0 0 0 1 o t f p 0 5 1 = v c c v 3 . 3 = t a 5 2 + = o c r l k 3 = ? k 7 o t , ? v 3 + m o r f d e r u s a e m v 3 + o t v 3 - r o v 3 - o t 40 3c l f p 0 0 5 2 o t f p 0 5 1 =
5 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation e m a nn o i t c n u f n i p r e b m u nr e b m u n r e b m u n r e b m u nr e b m u n e 3 0 2 3 p s + 1 c . 1 c , r o t i c a p a c p m u p - e g r a h c l a c i r t e m m y s e h t f o l a n i m r e t e v i t i s o p 1 + v. p m u p e g r a h c e h t y b d e t a r e n e g t u p t u o v 5 . 5 + d e t a l u g e r 2 - 1 c . 1 c , r o t i c a p a c p m u p - e g r a h c l a c i r t e m m y s e h t f o l a n i m r e t e v i t a g e n 3 + 2 c . 2 c , r o t i c a p a c p m u p - e g r a h c l a c i r t e m m y s e h t f o l a n i m r e t e v i t i s o p 4 - 2 c . 2 c , r o t i c a p a c p m u p - e g r a h c l a c i r t e m m y s e h t f o l a n i m r e t e v i t a g e n 5 - v. p m u p e g r a h c e h t y b d e t a r e n e g t u p t u o v 5 . 5 - d e t a l u g e r 6 r 1 n i. t u p n i r e v i e c e r 2 3 2 - s r 4 1 r 2 n i. t u p n i r e v i e c e r 2 3 2 - s r 3 1 r 1 t u o. t u p t u o r e v i e c e r s o m c / l t t 1 1 r 2 t u o. t u p t u o r e v i e c e r s o m c / l t t 0 1 t 1 n i. t u p n i r e v i r d s o m c / l t t 7 t 2 n i. t u p n i r e v i r d s o m c / l t t 8 t 3 n i. t u p n i r e v i r d s o m c / l t t 9 t 1 t u o. t u p t u o r e v i r d 2 3 2 - s r 7 1 t 2 t u o. t u p t u o r e v i r d 2 3 2 - s r 6 1 t 3 t u o. t u p t u o r e v i r d 2 3 2 - s r 5 1 d n g. d n u o r g 8 1 v c c . e g a t l o v y l p p u s v 5 . 5 + o t v 0 . 3 + 9 1 n w o d t u h s. p m u p e g r a h c d n a s r e v i r d n w o d t u h s o t w o l c i g o l y l p p a 0 2 v l n o i t c e l e s e g a t l o v y l p p u s l e v e l - c i g o l 2 1
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 6 figure 7. sp3203e pinout configuration t 1 in 1 2 3 4 17 18 19 20 5 6 7 16 15 14 shutdown v+ c1+ gnd v cc 8 9 10 11 12 13 t 3 in r 2 out t 2 in r 1 out v l sp3203e c 1 - c 2 + c 2 - v- t 1 out t 2 out t 3 out r 1 in r 2 in
7 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation figure 8. sp3203e typical operating circuit sp3203e 1 3 5 4 2 6 19 gnd t 1 in t 2 in c1+ c1- c2+ c2- v+ v- v cc 7 8 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 17 16 rs-232 outputs rs-232 inputs ttl/cmos inputs +3v to +5.5v 18 5k ? r 1 out 11 14 5k ? r 2 in r 2 out 10 13 ttl/cmos outputs r 1 in t 2 out t 1 out shutdown 20 12 v l t 3 in 9 15 t 3 out
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 8 description the sp3203e is a 3-driver/2-receiver device that can be operated as a full duplex, rs-232 serial transceiver with the 3rd driver acting as a control line allowing a ring indicator (ri) signal to alert the uart on the pc. this transceiver meet the eia/tia-232 and itu- t v.28/v.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers, pda's and cell phones. the sp3203e devices feature sipex's proprietary and patented (u.s. # 5,306,954) on-board charge pump circuitry that generates 5.5v rs-232 voltage levels from a single +3.0v to +5.5v power supply. the sp3203e devices can operate at a minimum data range of 250kbps, driving a single driver. the sp3203e is a 3-driver/2-receiver device. theory of operation the sp3203e contains four basic circuit blocks: 1. drivers, 2. receivers, 3. a sipex proprietary charge pump and 4. v l circuitry. drivers the drivers are inverting level transmitters that convert ttl or cmos logic levels to 5.0v eia/ tia-232 levels with an inverted sense relative to the input logic levels. typically, the rs-232 output voltage swing is + 5.4v with no load and +5v minimum fully loaded. the driver outputs are protected against infinite short-circuits to ground without degradation in reliability. these drivers comply with the eia-tia-232f and all previous rs-232 versions. the driver output stages are turned off (high impedance) when the device is in shutdown mode. the drivers typically can operate at a data rate of 250kbps. the drivers can guarantee a data rate of 120kbps fully loaded with 3k ? in parallel with 1000pf, ensuring compatibility with pc-to-pc communication software. the slew rate of the driver output is internally limited to a maximum of 30v/ s in order to meet the eia standards (eia rs-232d 2.1.7, paragraph 5). the transition of the loaded output from high to low also meets the monotonicity requirements of the standard. the sp3203e driver can maintain high data rates up to 250kbps with a single driver loaded. figure 9 shows a loopback test circuit used to test the rs-232 drivers. figure 10 shows the test results of the loopback circuit with all three drivers active at 120kbps with typical rs-232 loads in parallel with 1000pf capacitors. figure 11 shows the test results where one driver was active at 250kbps and all three drivers loaded with an rs-232 receiver in parallel with a 1000pf capacitor. the transmitter inputs do not have pull-up resistors. connect unused inputs to ground or v l receivers the receivers convert 5.0v eia/tia-232 levels to ttl or cmos logic output levels. receivers are disabled when in shutdown. the truth table logic of the sp3203e driver and receiver outputs can be found in table 1. since receiver input is usually from a transmis- sion line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mv. this ensures that the receiver is immune to noisy transmission lines. should an input be left un- connected, an internal 5k ? pulldown resistor to ground will commit the output of the receiver to a high state. charge pump the charge pump is a sipex?atented design (u.s. #5,306,954) and uses a unique approach compared to older less?fficient designs. the charge pump still requires four external capacitors, but uses a four?hase voltage shifting technique to attain symmetrical 5.5v power supplies. the internal power supply
9 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation consists of a regulated dual charge pump that provides output voltages of 5.5v regardless of the input voltage (v cc ) over the +3.0v to +5.5v range. this is important to maintain compliant rs-232 levels regardless of power supply fluctuations. the charge pump operates in a discontinuous mode using an internal oscillator. if the output voltages are less than a of 5.5v, the charge pump is enabled. if the output voltages exceed a of 5.5v, the charge pump is disabled. this oscillator controls the four phases of the voltage shifting (figure 12). a description of each phase follows. v ss charge storage-phase 1(figure 13) during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to v cc . c l + is then switched to gnd and the charge in c 1 is transferred to c 2 . since c 2 + is connected to v cc , the voltage potential across capacitor c 2 is now 2 times v cc . table 1. shutdown truth table. (note: when device in shutdown, the sp3203e's charge pump is turned off and v+ decays to v cc. v- is pulled to ground and the transmitter outputs are disabled as high impendance). figure 9. loopback test circuit for rs-232 driver data transmission rates v ss transfer-phase 2 (figure 14) phase two of the clock connects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to gnd. this transfers a negative generated voltage to c 3 . this generated voltage is regulated to a minimum voltage of -5.5v. simultaneous with the transfer of the voltage to c 3 , the positive side of capacitor c 1 is switched to v cc and the negative side is connected to gnd . v dd charge storage-phase 3 (figure 15) the third phase of the clock is identical to the first phase ?the charge transferred in c 1 pro- figure 10. loopback test circuit result at 120kbps (all drivers fully loaded) figure 11. loopback test circuit result at 250kbps (all drivers fully loaded) sp3203e 1 3 5 4 2 6 19 gnd t 1 in t x in c1+ c1- c2+ c2- v+ v- v cc 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f ttl/cmos inputs +3v to +5v 18 shutdown 20 5k ? r 1 out 5k ? r x in r x out ttl/cmos outputs r 1 in t x out t 1 out v cc 1000pf 1000pf 12 v l +3v to +5.5v ch1 ch3 3 1 2 t t t t [] t1 in t1 out r1 out 5.00v ch2 5.00v m 5.00 s ch1 0v 5.00v 3 1 2 t t t t [] t1 in t1 out r1 out ch1 ch3 5.00v ch2 5.00v m 2.50 s ch1 0v 5.00v e 3 0 2 3 p s : e c i v e d n w o d t u h st x t u or x t u oe g r a h c p m u p 0z - h g i hz - h g i he v i t c a n i 1e v i t c ae v i t c ae v i t c a
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 10 duces ? cc in the negative terminal of c 1 , which is applied to the negative side of capacitor c 2 . since c 2 + is at v cc , the voltage potential across c 2 is 2 times v cc . v dd transfer-phase 4 (figure 16) the fourth phase of the clock connects the nega- tive terminal of c 2 to gnd, and transfers this positive generated voltage across c 2 to c 4 , the v dd storage capacitor. this voltage is regulated to +5.5v. at this voltage, the internal oscillator is disabled. simultaneous with the transfer of the voltage to c 4 , positive side of capacitor c 1 is switched to v cc and the negative side is con- nected to gnd, allowing the charge pump cycle to begin again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. s ince both v + and v are separately generated from v cc , in a no?oad condition, v + and v will be symmetrical. older charge pump approaches that generate v from v + will show a decrease in the magnitude of v compared to v + due to the inherent ineffiencies in the design. the clock rate for the charge pump is typically operates at 250khz. the external capacitors are usually 0.1 f with a 16v breakdown voltage rating. v l supply level current rs-232 serial tranceivers are designed with fixed 5v or 3.3v ttl input/output voltages levels. the v l function in the sp3203e allows the end user to set the ttl input/output voltage levels independent of v cc . by connecting v l to the main logic bus of system, the ttl input/ output limits and threshold are reset to interface with the on board low voltage logic circuity. : e l b a t n o i t c e l e s r o t i c a p a c v c c ) v (( 1 c ) f( 4 c - 2 c ) f 6 . 3 o t 0 . 31 . 01 . 0 5 . 5 o t 5 . 47 4 0 . 03 3 . 0 5 . 5 o t 0 . 32 2 . 01
11 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation figure 14. charge pump ?phase 3 - v ss charge transfer figure 12. charge pump waveforms figure 15. charge pump ?phase 2 - v dd charge storage figure 16. charge pump ?phase 1 - v dd charge transfer figure 13. charge pump ?phase 4 - v ss charge storage ch1 2.00v ch2 2.00v m 1.00 s ch1 1.96v 2 1 t t [] t 2 +6v a) c 2+ b) c 2 - -6v 0v 0v
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 12 figure 17. circuit for the connectivity of the sp3203e with a db-9 connector 6 7 8 9 1 2 3 4 5 db-9 connector 6. dce ready 7. request to send 8. clear to send 9. ring indicator db-9 connector pins: 1. received line signal detector 2. received data 3. transmitted data 4. data terminal ready 5. signal ground (common) sp3203e 1 3 5 4 2 6 19 gnd c1+ c1- c2+ c2- v+ v- v cc 7 8 9 11 10 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 17 16 15 14 13 18 t 1 in r 1 out r 1 in t 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 2 out 12 v l shutdown 20
13 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation esd tolerance the sp3203e incorporates ruggedized esd cells on all driver output and receiver input pins. the improved esd tolerance is at least 15kv with- out damage nor latch-up. there are different methods of esd testing applied: a) mil-std-883, method 3015.7 b) iec1000-4-2 air-discharge c) iec1000-4-2 direct contact the human body model has been the generally accepted esd testing method for semiconductors. this method is also specified in mil-std-883, method 3015.7 for esd testing. the premise of this esd test is to simulate the human body? potential to store electro-static energy and discharge it to an integrated circuit. the simulation is performed by using a test model as shown in figure 18. this method will test the ic? capability to withstand an esd transient during normal handling such as in manufacturing areas where the ics tend to be handled frequently. the iec-1000-4-2, formerly iec801-2, is generally used for testing esd on equipment and systems. for system manufacturers, they must guarantee a certain amount of esd protection since the system itself is exposed to the outside environment and human presence. the premise with iec1000-4-2 is that the system is required to withstand an amount of static electricity when esd is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. the transceiver ic receives most of the esd current when the esd source is applied to the connector pins. the test circuit for iec1000-4-2 is shown on figure 19. there are two methods within iec1000-4-2, the air discharge method and the contact discharge method. with the air discharge method, an esd voltage is applied to the equipment under test (eut) through air. this simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. the high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. this energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. variables with an air discharge such as approach speed of the object carrying the esd potential to the system and humidity will tend to change the discharge current. for example, the rise time of the discharge current varies with the approach speed. the contact discharge method applies the esd current directly to the eut. this method was devised to reduce the unpredictability of the esd arc. the discharge current rise time is constant since the energy is directly transferred without the air-gap arc. in situations such as hand held systems, the esd charge can be directly discharged to the equipment from a person already holding the equipment. the current is transferred on to the keypad or the serial port of the equipment directly and then travels through the pcb and finally to the ic. the circuit model in figures 18 and 19 represent the typical esd testing circuit used for all three methods. the c s is initially charged with the dc figure 18. esd test circuit for human body model r r c c c c s s r r s s sw1 sw1 sw2 sw2 r c device under t est dc power source c s r s sw1 sw2
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 14 device pin human body iec1000-4-2 tested model air discharge direct contact level driver outputs 15kv 15kv 8kv 4 receiver inputs 15kv 15kv 8kv 4 power supply when the first switch (sw1) is on. now that the capacitor is charged, the second switch (sw2) is on while sw1 switches off. the voltage stored in the capacitor is then applied through r s , the current limiting resistor, onto the device under test (dut). in esd tests, the sw2 switch is pulsed so that the device under test receives a duration of voltage. for the human body model, the current limiting resistor (r s ) and the source capacitor (c s ) are 1.5kw an 100pf, respectively. for iec-1000-4- 2, the current limiting resistor (r s ) and the source capacitor (c s ) are 330w an 150pf, respectively. the higher c s value and lower r s value in the iec1000-4-2 model are more stringent than the human body model. the larger storage capacitor injects a higher voltage to the test point when sw2 is switched on. the lower current limiting resistor increases the current charge onto the test point. figure 20. esd test waveform for iec1000-4-2 t=0ns t=30ns 0a 15a 30a t ? i ? figure 19. esd test circuit for iec1000-4-2 table 2. transceiver esd tolerance levels r r s s and and r r v v add up to 330 add up to 330 ? ? f f or iec1000-4-2. or iec1000-4-2. r s and r v add up to 330 ? for iec1000-4-2. contact-discharge module contact-discharge module r r v v r r c c c c s s r r s s sw1 sw1 sw2 sw2 r c device under t est dc power source c s r s sw1 sw2 r v contact-discharge module
15 date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation gage plane 1.0 oia e 0.169 (4.30) 0.177 (4.50) 0.252 bsc (6.4 bsc) 0?-8? 12?ref 0.039 (1.0) e/2 0.039 (1.0) 0.126 bsc (3.2 bsc) 0.007 (0.19) 0.012 (0.30) 0.033 (0.85) 0.037 (0.95) 0.002 (0.05) 0.006 (0.15) 0.043 (1.10) max ( 3) 1.0 ref 0.020 (0.50) 0.026 (0.75) ( 1) 0.004 (0.09) min 0.004 (0.09) min 0.010 (0.25) ( 2) 0.008 (0.20) dimensions in inches (mm) minimum/maximum symbol 20 lead d 0.252/0.260 (6.40/6.60) e 0.026 bsc (0.65 bsc) d package: 20 pin tssop
date: 02/24/05 sp3203e, 3v rs232 serial transceiver with logic selector and 15kv esd ? copyright 2005 si pex corporation 16 model temperature range package types sp3203ecy 0 c to +70 c 20-pin tssop sp3203ecy/tr 0 c to +70 c 20-pin tssop sp3203eey -40 c to +85 c 20-pin tssop sp3203eey/tr -40 c to +85 c 20-pin tssop ordering information sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. corporation analog excellence sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 sales office 22 linnell circle billerica, ma 01821 tel: (978) 667-8700 fax: (978) 670-9001 e-mail: sales@sipex.com available in lead free packaging. to order add "-l" suffix to part number. example: sp3203eey/tr = standard; SP3203EEY-L/tr = lead free tr = tape and reel pack quantity is 1500 for tssop. click here to order samples

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